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description the CXB1563Q achieves the 2r optical-fiber communication receiver functions (reshaping and regenerating) on a single chip. this ic is also equipped with the signal interruption alarm output function, which is used to discriminate the existence of data input. features auto-offset canceler circuit signal interruption alarm output 2-level switching function of identification maximum voltage amplitude for alarm block single 5v power supply applications sonet/sdh : 622.08mb/s fiber channel : 531.25mb/s absolute maximum ratings supply voltage v cc ?v ee ?.3 to +7.0 v storage temperature tstg ?5 to +150 ? input voltage difference : i v d ?v d i vdif 0.0 to +2.5 v sw input voltage vi v ee to v cc v output current (continuous) i o 0 to 50 ma (surge current) 0 to 100 ma recommended operating conditions supply voltage v cc ?v ee 5.00.5 v termination voltage (for data/alarm) v cc ?v t1 1.8 to 2.2 v termination voltage (for alarm 2) v t2 v ee v termination resistance (for data/alarm) r t1 45 to 55 ? termination resistance (for alarm 2) r t2 460 to 560 ? operating temperature ta ?0 to +85 ? structure bipolar silicon monolithic ic ?1 CXB1563Q e95710b1z-ps 2r ic for optical fiber communication receiver sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 32 pin qfp (plastic)
?2 CXB1563Q block diagram and pin configuration 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 peak hold ? v peak hold alarm block limiting amplifier block r1 r1 r2 r2 q vccda sd q sd vccd vccda n.c. n.c. cap3 cap2 down up vcca tm vccd v ee d vcca v ee a cap1 r2k r1k vcca vcca v ee i sw d d cap1 n.c. r3 r4 v cc a n.c.
3 CXB1563Q pin description pin no. 1,2 v cc a 0v positive power supply for analog block. switches the identification maximum voltage amplitude. high voltage when open; the identification maximum voltage amplitude becomes 50mvp-p. low voltage when connecting this pin to v ee ; the amplitude becomes 20mvp-p. 3v ee i 5v 4 sw 0v (open) or 5v limiting amplifier block input. be sure to make this input with ac coupled. positive power supply for analog block. pins 8 and 11 connect a capacitor which determines the cut-off frequency for feedback block, and 1k ? is connected between pins 8 and 9; 2k ? between pins 10 and 11. a resistor which is to be inserted in parallel with a capacitor can be selected 5 ways by external wiring, and dc feedback can be varied. 5 d 1.3v 0.9v to 1.7v 0.9v to 1.7v 6 d 1.3v 7 v cc a 0v 8 cap1 1.8v 9 r1k 10 r2k 11 cap1 1.8v generates the default voltage between up and down. the voltage (8.0mv for input conversion) can be generated between up and down (pins 30 and 31) as alarm setting level by connecting this pin to v ee a. symbol typical pin voltage (v) dc ac equivalent circuit description 150k 100k v ref v ee a v cc a 4 31 30 vcca v ee a sw 993 110.3 110.3 vcs 3 v cc a v ee a 200 200 1.5k 1.5k 10k 10k 100p 200 200 2k 1k 5 6 11 10 9 8
4 CXB1563Q 12 13 14 15 v ee a v cc a v ee d v cc d 5v 0v 5v 0v 0.9v to 1.7v negative power supply for analog block. positive power supply for analog block. negative power supply for digital block. positive power supply for digital block. 16 tm 3.4v 18 q 0.9v to 1.7v 19 q positive power supply for output buffer. 20 v cc da chip temperature monitor. 17 n.c no connected. data signal output. terminate this pin in 50 ? at v tt = 2v. 0.9v to 1.7v 21 sd alarm signal output. terminate this pin in 50 ? at v tt = 2v. dc ac 14 16 0.9v to 1.7v 22 sd 23 24 25 26 27 vccda vccd n.c n.c n.c positive power supply for digital block. positive power supply for digital block. no connected. 0v 0v 0v v ee d v cc da 19 18 v ee d v cc da 21 22 pin no. symbol typical pin voltage (v) equivalent circuit description
5 CXB1563Q dc ac 28 cap3 1.8v 29 cap2 1.8v connects a peak hold circuit capacitor for alarm block. 470pf should be connected to vcca each. cap2 pin peak hold capacitor connection for alarm level setting block. cap3 pin peak hold capacitor connection for limiting amplifier signal. 10p 10p v cc a v ee a 80 5a 5a 80 29 28 30 down 0.84v (for v ee i = 5v) 31 up 0.8v (for v ee i = 5v) 32 vcca 0v positive power supply for analog block. connects a resistor for alarm level setting. default voltage can be generated without an external resistor by shorting the v ee i pin to v ee a. 31 30 vcca v ee a sw 993 110.3 110.3 vcs 3 pin no. symbol typical pin voltage (v) equivalent circuit description
6 CXB1563Q power supply q/q sd/sd high output voltage q/q sd/sd low output voltage sd/sd high output voltage 2 sd/sd low output voltage 2 sw high input voltage sw low input voltage sw high input current sw low input current d/d input resistance internal resistance 1 for alarm level setting internal resistance 2 for alarm level setting pare ratio of internal resistance 2 for alarm level setting resistance between cap1 and r1k resistance between cap1 and r2k electrical characteristics dc characteristics (v cc = gnd, v ee = 5v10%, ta = 40 to +85 c, v cc = v cc d, v cc da, v cc a v ee = v ee d, v ee a) item i ee v oh v ol v ohb v olb v ih v il i ih i il rin ra1 ra2a, b ra2 r3 r4 r t1 = 50 ? , v t1 = 2v termination r t1 = 50 ? , v t1 = 2v termination, ta = 0 to 85 c r t2 = 510 ? , v ee termination, ta = 0 to 85 c refer to fig. 3. refer to fig. 3. ra2a/ra2b 50 1025 1810 1075 1860 1900 v ee 60 1125 745 82.7 0.97 745 1489 37 1500 993 110.3 993 1986 28 880 1620 830 1570 0 2500 2 1875 1241 137.9 1.03 1241 2482 ma mv a ? ? symbol min. typ. max. unit conditions
7 CXB1563Q maximum input voltage amplitude amplifier gain (in limiting amplifier) identification maximum voltage amplitude of alarm level hysteresis width sd response assert time sd response deassert time sd response assert time for alarm level default sd response deassert time for alarm level default alarm setting level for default propagation delay time q/q rise time q/q fall time sd/sd rise time sd/sd fall time ac characteristics (v cc = gnd, v ee = 5v10%, ta = 40 to +85 c, v cc = v cc d, v cc da, v cc a v ee = v ee d, v ee a) item vmax gv vmina1 vmina2 ? p tas tdas tasd tdasd vdef t pd tr_q tf_q tr_sd tf_sd single-ended input sw pad: low, single-ended input sw pad: open high, single-ended input low high ? 1 high low ? 2 low high ? 3 high low ? 4 up/down pins; open, connect v ee i to v ee . d to q r t1 = 50 ? , v t1 = 2v termination, v ee = 5v, ta = 0 to 85 c 20% to 80% 1600 40 20 50 4 0 2.3 0 2.3 6.6 0.4 250 250 0.45 0.45 6 8.0 1.0 7 100 100 100 100 9.3 1.6 450 450 1.6 1.6 mvp-p db mvp-p db s mv ns ps ns symbol min. typ. max. unit conditions ? 1 v up v down = 100mv, vin = 100mvp-p (single ended), sw pin: high peak hold capacitance (cap2, cap3 pins) of 470pf; connect v ee i to v ee . ? 2 v up v down = 100mv, vin = 1vp-p (single ended), sw pin: high peak hold capacitance (cap2, cap3 pins) of 470pf; connect v ee i to v ee . ? 3 vin = 50mvp-p (single ended), sw pin: low peak hold capacitance (cap2, cap3 pins) of 470pf; connect v ee i to v ee . ? 4 vin = 1vp-p (single ended), sw pin: low peak hold capacitance (cap2, cap3 pins) of 470pf; connect v ee i to v ee .
8 CXB1563Q dc electrical characteristics measurement circuit v v v v 51 51 51 51 c3 c3 v v v v vs vd c1 c1 a v ee 5v v c2 v 2v v t1 v a 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 peak hold ? v peak hold alarm block limiting amplifier block r1 r1 r2 r2 r3 r4
9 CXB1563Q ac electrical characteristics measurement circuit z0 = 50 z0 = 50 z0 = 50 z0 = 50 oscilloscope 50 ? input 0.22f 0.022f 0.022f v ee v cc 3v +2v v r ex1 r ex2 470pf 470pf 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 peak hold ? v peak hold alarm block limiting amplifier block r1 r1 r2 r2 r3 r4 51 51
10 CXB1563Q application circuit c2 0.22f c1 0.022f v ee 5v c3 470pf c1 0.022f c3 470pf 51 51 51 51 v t1 2v 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 peak hold ? v peak hold alarm block limiting amplifier block r1 r1 r2 r2 r3 r4 51 51 application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
11 CXB1563Q c1 c1 c2 r1 r1 r2 r2 to ic interior d r3 r4 5 6 8 9 10 11 fig. 1 f1 f2 frequency gain feedback frequency response amplifier frequency response fig. 2 notes on operation 1. limiting amplifier block the limiting amplifier block is equipped with the auto-offset canceler circuit. when external capacitors c1 and c2 are connected as shown in fig. 1, the dc bias is set automatically in this block. external capacitor c1 and ic internal resistor r1 determine the low input cut-off frequency f2 as shown in fig. 2. similarly, external capacitor c2 and ic internal resistor r2 determine the high cut-off frequency f1 for dc bias feedback. since peaking characteristics may occur in the low frequency area of the amplifier gain characteristics depending on the f1/f2 combination, set the c1 and c2 so as to avoid the occurrence of peaking characteristics. the target values of r1 and r2 and the typical values of c1 and c2 are as indicated below. when a single-ended input is used, provide ac grounding by connecting pin 6 to a capacitor which has the same capacitance as capacitor c1. r1 (internal): 1.5k ? r2 (internal): 10k ? f2: 4.8khz f1: 72hz c1 (external): 0.022f c2 (external): 0.22f 1k ? is incorporated between pins 8 and 9; 2k ? between pins 10 and 11. a resistance value which is to be inserted in parallel with a capacitor f2 can be selected 5 ways ( , 3k ? , 2k ? , 1k ? , 1k//2k ? ) by external wiring, and dc feedback can be varied.
12 CXB1563Q 2. alarm block in order to operate the alarm block, give the voltage difference between pins 30 and 31 to set an alarm level and connect the peak hold capacitor c3 shown in fig. 3. this ic has two setting methods of alarm level; one is to connect v ee to pin 3 and leave pins 30 and 31 open to set an alarm level default value (8mv for input conversion). the other is to connect pin 3 to v ee and set a desired alarm level using the external resistors r ex1 and r ex2 and r ex3 shown in fig. 3. connect r ex1 between pins 30 and 31, or between pin 30 and v cc when less alarm level is desired to be set than its default value; connect r ex2 between pin 31 and vcc potential when more alarm level is desired to be set than its default value. however, the pin 31 voltage must be higher than that of pin 30. refer to figs. 5, 8 to 13 for this alarm level setting. this ic also features two-level setting of identification maximum voltage amplitude. the amplitude is set to 50mvp-p when pin 4 is left open (high level) and it is set to 20mvp-p when pin 4 is low level. therefore, noise margin can be increased by setting pin 4 to low level when small signal is input. the relation of input voltage and peak hold output voltage is shown in fig. 6. in the relation between the alarm setting level and hysteresis width, the hysteresis width is designed to maintain a constant gain (design target value: 6db) as shown in fig. 4. the c3 capacitance value should be set so as to obtain desired assert time and deassert time settings for the alarm signal. the electrical characteristics for the sd response assert and deassert times are guaranteed only when the waveforms are input as shown in the timing chart of fig. 7. the typical values of r ex1 , r ex2 , r ex3 and c3 are as follows: (approximately 10pf capacitor is built in pins 28 and 29 each.) r ex1 : 217 ? (when the alarm level is set to 4mv for input conversion.) r ex2 : 634 ? (when the alarm level is set to 19mv for input conversion.) r ex3 : 4k ? (when the alarm level is set to 4mv for input conversion.) c3 : 470pf the table below shows the alarm logic. from limiting amplifier peak hold sd sd vcca 10p vcca 10p vcc c3 vcc peak hold ra2b 110.3 ra1 v cc a ic interior ic exterior ra1, ra2a and ra2b values are typical values. c3 30 31 ra2a 110.3 993 vcs ? v 31 30 29 28 vcc r ex1 r ex2 3 4 3 vcc r ex3 optical signal input state signal input signal interruption high level low level low level high level sd sd fig. 3
13 CXB1563Q 3db 3db alarm setting input level hysteresis input electrical signal amplitude sd output high level low level small large v das v as v das deassert level v as assert level v as v das v as , v das [mv] voltage between pins 30 and 31 [mv] 25 20 15 10 5 0 0 20 40 60 80 100 aaa aaa sw = high sw = low fig. 4 fig. 5 peak hold output voltage 02 0 5 0 input voltage [mvp-p] sw open high sw low fig. 6 assert time alarm setting level hysteresis width data input (d) deassert time data output (q) alarm output (sd) fig. 7
14 CXB1563Q 3. others pay attention to handling this ic because its electrostatic discharge strength is weak. 1000 1200 1400 1600 1800 50 25 0 25 50 75 100 125 tj [ c] tm-v ee [mv] tm pin temperature characteristics aaaaaaaaa aaaaaaaaa aaaaaaaaa aaaaaaaaa aaaaaaaaa aaaaaaaaa aaaaaaaaa a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a aa aa aa aa aa aa aa a a a a a a a a a a a a a a iin=100 a iin=1ma iin=5ma rex1 [ ? ] 0 2000 400 800 1200 1600 5 40 35 30 25 20 15 10 vup-vdown [mv] 40 c 27 c 85 c 125 c rex1-vud temperature characteristics data fig. 8 fig. 9 rex2-vud temperature characteristics data rex2 [ ? ] 0 7000 1000 3000 4000 5000 40 130 120 110 100 90 80 60 vup-vdown [mv] 2000 50 40 c 27 c 85 c 125 c 6000 70 rex3 [k ? ] 030 5152025 0 40 35 30 25 20 15 10 vup-vdown [mv] 40 c 27 c 85 c 125 c 10 5 rex3-vud temperature characteristics data fig. 10 fig. 11 fig. 12 fig. 13 aaaaaaaaa aaaaaaaaa aaaaaaaaa aaaaaaaaa aaaaaaaaa aaaaaaaaa aaaaaaaaa aaaaaaaaa 0 2 4 6 8 0 400 800 1200 1600 2000 rex1 [ ? ] alarm setting level [mv] alarm setting level vs. rex1 a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a ta = 27 c 10 12 14 16 18 20 22 0 1000 2000 3000 4000 5000 6000 7000 rex2 [ ? ] alarm setting level [mv] alarm setting level vs. rex2 aaaaaaaaa aaaaaaaaa aaaaaaaaa aaaaaaaaa aaaaaaaaa a a a a a a a a a a a a a a a a a a a a a aa aa aa aa aa aa aa a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a aa aa aa aa aa aa aa ta = 27 c
15 CXB1563Q example of representative characteristics 10 9 10 8 10 7 10 6 10 5 10 4 1.8 2 2.2 2.4 2.6 2.8 3 data input level [mvp-p] bit error rate bit error rate vs. data input level aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a aa aa aa aa aa aa aa a a a a a a a 10 11 10 10 v ee = 5.0v ta = 27 c d = 622.08mbps pattern : prbs2 23 1 0 10 20 30 40 50 60 70 80 1 10 100 1000 data input level [mvp-p] output rms jitter [ps] output rms jitter vs. data input level aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa a a a a a a a aa aa aa aa aa aa aa a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a aa aa aa aa aa aa aa a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a v ee = 5.0v ta = 27 c d = 622.08mbps pattern: prbs2 23 1 fig. 14 q output waveform v ee = 5.0v ta = 27 c d = 622.08mbps vin = 3mvp-p, single input pattern : prbs2 23 1 22.3500ns 19.8500ns 24.8500ns ch. 1 = 200.0mv/div timebase = 500ps/div offset = 680.0mv delay = 22.3500ns fig. 16 fig. 15
16 CXB1563Q package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42 / copper alloy 32pin qfp (plastic) 9.0 0.2 7.0 ?0.1 1.5 ?0.15 (8.0) 0.1 ?0.1 + 0.2 + 0.35 + 0.3 0.50 0? to 10? 0.8 b 1 8 9 32 16 17 24 25 m 0.24 0.2g qfp-32p-l01 p-qfp32-7x7-0.8 0.1 b = 0.30 ?0.10 ( 0.30) (0.127) + 0.15 detail a : solder a 0.127 ?0.05 + 0.10 package structure sony corporation lead plating specifications item lead material 42 alloy solder composition sn-bi bi:1-4wt% plating thickness 5-18 m spec. kokubu ass'y sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42 / copper alloy 32pin qfp (plastic) 9.0 0.2 7.0 0.1 1.5 0.15 (8.0) 0.1 0.1 + 0.2 + 0.35 + 0.3 0.50 0 ? to 10 ? 0.8 b 1 8 9 32 16 17 24 25 m 0.24 0.2g qfp-32p-l01 p-qfp32-7x7-0.8 0.1 b = 0.30 0.10 ( 0.30) (0.127) + 0.15 detail a : solder a 0.127 0.05 + 0.10 package structure

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